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BCA Gujarat University Study Material - Notes - Guide

Study Material Computer Organization and Microprocessor SY BCA

Chapter 7. Main Memory Desing

1 Define cache hit and cache miss. (1 Marks)(Guj. Uni. March 2008)
Answer
2 Draw the diagram of Memory Heirarchy. (1 Marks)(Guj. Uni. March 2008)
3 State the steps the processor performs during Memory Write Operation. (2 Marks)(Guj. Uni. March 2008)
4 Write a note on Auxiliary memory and Virtual Memory (2 Marks)(Guj. Uni. March 2008)
5 State the difference between SRAM and DRAM. (2 Marks)(Guj. Uni. March 2008)
6 Define Access Time, Recovery Time, Cycle Time and stae the relationship between the three. (2 Marks)(Guj. Uni. March 2008)
Answer
Cycle Time : the cycle time is the total time including access time and recovery time.
7 What is meant by cache replacement? Explain any two cache replacement algorithms. (2 Marks)(Guj. Uni. March 2008)
8 Explain difference between write-Through and write back policy. (2 Marks)(Guj. Uni. March 2008)
9 Write note on Main Memory. (2 Marks)(Guj. Uni. March 2008)
10 Explain any two Memory access methos. (2 Marks)(Guj. Uni. March 2008)
11 11. Write a note on memory technology. (2 Marks)(Guj. Uni. March 2008)
12 Explain the concept of main memory with diagram. (5 marks) (Chimanbhai Patel Collage, Seecond Test 2008)
13 Write a short note on Auxilary memory. (5 marks) (Chimanbhai Patel Collage, Seecond Test 2008)
14 Explain Cache write policy. (5 marks) (Chimanbhai Patel Collage, Seecond Test 2008)
15 Explain associative mapping. (5 marks) (Chimanbhai Patel Collage, Seecond Test 2008)
16 Explain Virtual memory. (5 marks) (Chimanbhai Patel Collage, Seecond Test 2008)
17 Explain merits and demerits of all mapping technique.
18 Explain memory hierarchy with the help of diagrams. (5 marks) (HL collage Seecond Test 2008)
19 A CPU has 16 bit address for memory addressing, then what is the memory addressability of the CPU. (5 marks) (HL collage Seecond Test 2008)
20 Draw the diagram of Ashynchronous memory interface. (5 marks) (HL collage Seecond Test 2008)
21 Define latency in memory parameter. (1 mark) (HL collage Seecond Test 2008)
Answer
In some types of emory such as hard disk, the internal organization is such that the first access to any location has longer access time where as the successive locations hsave shorter access time. The latency is the access time for the first access in a series of access.
22 Define Flash memory. (1 mark) (HL collage Seecond Test 2008)
23 Define Write through policy.
24 State the difference between Auxiliary memory and Main memory.
25 Explain PROM and EPROM.
26 State the difference between SRAM and DRAM.
27 Explain the following terms : cache hit, cache miss, miss penality and hit ratio.
28 List the technique for resolving the problem of main memory spee and explain the instruction prefetch.
29 Explain all four cache replacement algorithm.
17 Explain merits and demerits of all mapping technique.